At 508, the level shifter provides the amplitude shifted signal to a system controller through a current protection resistor. The current protection resistor can dissipate a voltage provided by a transmitted signal from timing controller in the event of mistaken simultaneous signal transmission and receipt.

At 510, a system controller processes a received clock pulse. The clock pulse can provide 1 pulse per second (PPS) or 10 MHz signal in reference to sections 19.2 and 20 of ITU-T G.703 (2016). The system controller can align its timing circuit such as a phase locked loop with the clock pulse to achieve clock synchronization with another device. Use of IEEE 1588 PTP timing synchronization can be used. The system controller has the right time so it can communicate time to another device under precision time protocol (PTP). A delay due to use of current protection resistor can be taken into account by adjusting a time stamp of a received clock pulse to be earlier in time by an amount of the delay.

FIG. 5B depicts a process to transmit a signal using a timing synchronization of circuit of a network interface. At 550, a timing transmit/receive circuit is configured to enable a signal transmit circuit path. For example, a user or software (e.g., driver) can configure a timing synchronization of circuit of a network interface. For example, enablement can occur for a signal path through a parallel connected combination of buffer in series with protection resistors and a parallel connected combination of isolation switches.