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Bi-directional buffer with circuit protection time synchronization

專利號
US12200089B2
公開日期
2025-01-14
申請人
Intel Corporation(US CA Santa Clara)
發(fā)明人
April E. Fisher; Benjamin Cheong; Kevin Bross; Manishkumar T. Rana; Andrew M. Monk
IPC分類
H04L7/00
技術(shù)領(lǐng)域
or,tx,signal,sdp,sma,can,resistor,path,transmit,circuitry
地域: CA CA Santa Clara

摘要

Examples described herein are used in timing synchronization systems. A timing synchronization system provides circuits that support bi-directional half-duplex voltage signals (transmit or receive) but protect against incorrect input/output configuration whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port. The system provides configurable signal propagation by use of parallel connection of two or more buffer in series with a resistor. Various isolation circuitry and resistors can be used to protect against signal transmission during receive mode.

說明書

Some time-synchronization devices require a user to power down the system and have physical access to the device to manually configure the jumpers connected to the media for transmit or receive, which interrupts use of the network device, increases network down-time, and can disrupt network bandwidth. Moreover, jumpers can be easily misconfigured by the user, resulting in permanent physical damage to equipment and potential harm to the user.

Various embodiments provide circuits that support simultaneous bidirectional voltage signals (transmit and receive) but protect against incorrect input/output configuration (e.g., due to user error whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port) while providing a fast rise-time (e.g., single-digit nanoseconds) for signal propagation used for time synchronization. For example, if a cable is plugged into the wrong port, a signal can be received by the time-synchronization device from a port that is to transmit signals. Generally, protection that uses high resistances in a signal path against incorrect configuration and excessive current level will degrade the rise-time of a signal due to a higher resistor-capacitance (RC) time constant. Various embodiments manage rise-time of a signal and corresponding propagation delays by splitting the transmit circuits into multiple parallel signal paths to reduce the effective RC time constant. Various embodiments can permit use of a range of user-connected cables (e.g., types and lengths) with various exhibited capacitance values and control RC time constant to achieve desired signal propagation delay by controlling propagation delay by tuning the resistance and capacitance levels of multiple parallel signal paths.

權(quán)利要求

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