白丝美女被狂躁免费视频网站,500av导航大全精品,yw.193.cnc爆乳尤物未满,97se亚洲综合色区,аⅴ天堂中文在线网官网

Bi-directional buffer with circuit protection time synchronization

專利號
US12200089B2
公開日期
2025-01-14
申請人
Intel Corporation（US CA Santa Clara）
發(fā)明人
April E. Fisher; Benjamin Cheong; Kevin Bross; Manishkumar T. Rana; Andrew M. Monk
IPC分類
H04L7/00
技術領域
or,tx,signal,sdp,sma,can,resistor,path,transmit,circuitry
地域： CA CA Santa Clara

摘要

Examples described herein are used in timing synchronization systems. A timing synchronization system provides circuits that support bi-directional half-duplex voltage signals (transmit or receive) but protect against incorrect input/output configuration whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port. The system provides configurable signal propagation by use of parallel connection of two or more buffer in series with a resistor. Various isolation circuitry and resistors can be used to protect against signal transmission during receive mode.

說明書

Various embodiments permit software-based transmit or receive configuration of a time-synchronization device and do not require a user to manually change transmit or receive cables attached to the time-synchronization device.

Various embodiments support a voltage shift of a wide range of input signal voltage amplitudes (e.g., 1.65V to 5.5V or other ranges) by software-based control and without requiring manual configuration for the voltage shift.

Accordingly, various embodiments can be used with a network interface or systems that require high precision receipt or transmission of time-stamped signals, such as time-stamped signals compatible with IEEE 1588 (2008). For example, time-stamped signal can include Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp messages of IEEE 1588 (2008) and IEEE 802.1AS (2011).

權利要求

1
微信群二維碼
意見反饋