The first end (gate) of the first transistor Q1 is connected to the third node N3, the second end (drain) of the first transistor Q1 is connected to the second node N2, and the third end (source) of the first transistor Q1 is connected to the fourth node N4. The first end (gate) of the second transistor Q2 is connected to the fifth node N5, the second end (drain) of the second transistor Q2 is connected to the third node N3, and the third end (source) of the second transistor Q2 is connected to the sixth node N6. The first end (gate) of the third transistor Q3 is connected to the sixth node N6, the second end (drain) of the third transistor Q3 is connected to one end of the fifth resistor R5, and the third end (source) of the third transistor Q3 is connected to the fifth node N5 (in this embodiment, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all n-channel MOSFETs). The other end of the fifth resistor R5 is connected to the seventh node N7, and the seventh node N7 is connected to the power source positive electrode V+ of the power supplying module 11. The two ends of the second resistor R2 are connected to the seventh node N7 and the eighth node N8. The two ends of the first resistor R1 are connected to the fifth node N5 and the eighth node N8 respectively. The two ends of the third resistor R3 are connected to the first node N1 and the fourth node N4 respectively. The two ends of the fourth resistor R4 are connected to the second node N2 and the third node N3 respectively. The two ends of the sixth resistor R6 are connected to the fourth node N4 and the fifth node N5 respectively. The two ends of the seventh resistor R7 are connected to the first node N1 and the sixth node N6 respectively. The two ends of the first capacitor C1 are connected to the first node N1 and the fifth node N5 respectively. The two ends of the diode ZD are connected to the first node N1 and the eighth node N8 respectively.