Semiconductor devices with threshold voltage modulation layer
地域：
Hsin-Chu
摘要
A method comprises forming a first fin including alternating first channel layers and first sacrificial layers and a second fin including alternating second channel layers and second sacrificial layers, forming a capping layer over the first and the second fin, forming a dummy gate stack over the capping layer, forming source/drain (S/D) features in the first and the second fin, removing the dummy gate stack to form a gate trench, removing the first sacrificial layers and the capping layer over the first fin to form first gaps, removing the capping layer over the second fin and portions of the second sacrificial layers to from second gaps, where remaining portions of the second sacrificial layers and the capping layers form a threshold voltage (Vt) modulation layer, and forming a metal gate stack in the gate trench, the first gaps, and the second gaps.
說明書
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This application claims priority to U.S. Provisional Patent Application Ser. No. 63/182,662 entitled “Sheet Formation for Semiconductor Devices” filed on Apr. 30, 2021, the entire disclosure of which is incorporated herein by reference.
The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
權(quán)利要求
What is claimed is:1. A method, comprising:forming a first fin and a second fin protruding from a semiconductor substrate, wherein the first fin includes alternating first channel layers and first sacrificial layers, and wherein the second fin includes alternating second channel layers and second sacrificial layers; forming an isolation feature between the first fin and the second fin; forming a capping layer over the first fin, the second fin, and the isolation feature; forming a dummy gate stack over the capping layer; forming source/drain (S/D) features in the first fin and the second fin adjacent to the dummy gate stack; removing the dummy gate stack, thereby forming a gate trench; removing the first sacrificial layers and the capping layer over the first fin, thereby forming first gaps between the first channel layers; removing portions of the capping layer over the second fin and portions of the second sacrificial layers, thereby forming second gaps between the second channel layers, such that remaining portions of the second sacrificial layers and remaining portions of the capping layer form a threshold voltage (Vt) modulation layer, wherein the Vt modulation layer wraps around each of the second channel layers; and forming a metal gate stack in the gate trench, the first gaps, and the second gaps. 2. The method of claim 1 , wherein the capping layer includes Si1-xGex (0.4≤x≤1) and the second sacrificial layers include Si1-yGey (0≤y≤1), wherein x is different from y. 3. The method of claim 1 , wherein the forming of the Vt modulation layer includes:forming a silicon layer over the first fin and the second fin; and doping the silicon layer with germanium. 4. The method of claim 1 , wherein the removing of the portions of the capping layer over the second fin and the portions of the second sacrificial layers includes:forming a mask over the first fin after the removing of the capping layer over the first fin and the first sacrificial layers; removing portions of the capping layer on sidewalls of the second sacrificial layers; and removing portions of the second sacrificial layers, thereby forming the second gaps between the second channel layers. 5. The method of claim 1 , wherein the first fin is a portion of a pull-up transistor of a static random-access memory (SRAM) cell, and wherein the second fin is a portion of a pull-down transistor of the SRAM cell. 6. The method of claim 1 , wherein the forming of the metal gate stack includes:forming a gate dielectric layer wrapping around each of the first channel layers and the Vt modulation layer, thereby partially filling the first gaps and the second gaps; forming a work-function metal (WFM) layer over the gate dielectric layer, thereby completely filling the first gaps and the second gaps; forming a gate cap layer over the WFM layer; and forming a metal fill layer over the gate cap layer. 7. The method of claim 6 , wherein the WFM layer spans from the first fin to the second fin. 8. The method of claim 1 , further comprising:forming a protecting layer over the capping layer before the forming of the dummy gate stack; and removing the protecting layer after removing the dummy gate stack. 9. A method, comprising:providing a semiconductor substrate; alternately stacking first semiconductor layers and second semiconductors layers to form a semiconductor stack over the semiconductor substrate; patterning the semiconductor stack to form a first fin in a first region and a second fin parallel to the first fin in a second region; forming a dummy gate stack over the first fin and the second fin; epitaxially growing source/drain (S/D) features in S/D regions of the first fin and the second fin; removing the dummy gate stack to form a gate trench; removing the second semiconductor layers of the first fin and the second fin through the gate trench; forming a threshold voltage (Vt) modulation layer wrapping around each of the first semiconductor layers in the second region; and depositing a metal gate stack in the gate trench, the metal gate stack wrapping around each of the first semiconductor layers in the first region, the metal gate stack extending into gaps vertically between the first semiconductor layers in the second region and thereby dividing the Vt modulation layer as segments. 10. The method of claim 9 , wherein the Vt modulation layer includes Si1-xGex, wherein x is about 40% to about 50%, and wherein a thickness of the Vt modulation layer is about 10% to about 30% of a thickness of the first semiconductor layers wrapped thereover. 11. The method of claim 9 , wherein the forming of the Vt modulation layer includes:covering the first fin with a mask; depositing a silicon layer over each of the first semiconductor layers of the second fin; doping the silicon layer with germanium; and removing the mask. 12. The method of claim 9 , further comprising trimming the first semiconductor layers in the second region prior to the forming of the Vt modulation layer. 13. The method of claim 9 , wherein the first fin is from a pull-up transistor of a static random-access memory (SRAM) cell and the second fin is from a pull-down transistor of the SRAM cell. 14. The method of claim 9 , wherein the forming of the metal gate stack includes:forming a gate dielectric layer wrapping around each of the first semiconductor layers in the first region and each portion of the Vt modulation layer in the second region; forming a work-function metal (WFM) layer over the gate dielectric layer, wherein portions of the WFM layer are disposed between the first semiconductor layers of the first fin and the second fin; forming a liner layer over the WFM layer; and forming a metal fill layer over the liner layer. 15. A method, comprising:forming a first fin and a second fin protruding from a semiconductor substrate, wherein the first fin includes alternating first channel layers and first sacrificial layers, and wherein the second fin includes alternating second channel layers and second sacrificial layers; forming a capping layer on top and sidewall surfaces of the first fin and the second fin; forming a dummy gate stack over the capping layer; forming gate spacers on sidewalls of the dummy gate stack; removing the dummy gate stack, thereby forming a gate trench; removing the capping layer from the first fin and removing the first sacrificial layers; partially removing the capping layer from the second fin and partially removing the second sacrificial layers, such that remaining portions of the capping layer and remaining portions of the second sacrificial layers form a threshold voltage modulation layer wrapping around each of the second channel layers; and forming a metal gate stack in the gate trench. 16. The method of claim 15 , wherein a thickness of the threshold voltage modulation layer is about 10% to about 30% of a thickness of the second channel layers. 17. The method of claim 15 , wherein the threshold voltage modulation layer includes Si1-xGex, wherein x is about 40% to about 100%. 18. The method of claim 15 , wherein the first channel layers are portions of a pull-up transistor of a static random-access memory (SRAM) cell, and the second channel layers are portions of a pull-down transistor of the SRAM cell. 19. The method of claim 15 , wherein a thickness of a single one of the first channel layers equals to a sum of a thickness of a single one of the second channel layers and two times of a thickness of the threshold voltage modulation layer. 20. The method of claim 15 , further comprising:forming an isolation feature between the first fin and the second fin, wherein the forming of the capping layer includes depositing the capping layer on a top surface of the isolation feature.
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