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Semiconductor devices with threshold voltage modulation layer

專利號
US12213297B2
公開日期
2025-01-28
申請人
Taiwan Semiconductor Manufacturing Company, Ltd.（TW Hsinchu）
發(fā)明人
Shih-Hao Lin; Chih-Hsiang Huang; Shang-Rong Li; Chih-Chuan Yang; Jui-Lin Chen; Ming-Shuan Li
IPC分類
H01L21/8238; H01L21/02; H01L21/28; H01L29/06; H01L29/423; H01L29/49; H01L29/66; H01L29/786; H10B10/00
技術(shù)領(lǐng)域
layer,fins,wfm,layers,gate,vt,capping,in,channel,stacks
地域： Hsin-Chu

摘要

A method comprises forming a first fin including alternating first channel layers and first sacrificial layers and a second fin including alternating second channel layers and second sacrificial layers, forming a capping layer over the first and the second fin, forming a dummy gate stack over the capping layer, forming source/drain (S/D) features in the first and the second fin, removing the dummy gate stack to form a gate trench, removing the first sacrificial layers and the capping layer over the first fin to form first gaps, removing the capping layer over the second fin and portions of the second sacrificial layers to from second gaps, where remaining portions of the second sacrificial layers and the capping layers form a threshold voltage (Vt) modulation layer, and forming a metal gate stack in the gate trench, the first gaps, and the second gaps.

說明書

As integrated circuit (IC) technologies progress towards smaller technology nodes, the complex patterning process of forming the metal gates and the metal gate boundary diffusion between different types of metal-oxide-semiconductor field-effect transistor (MOSFETs) may have serious bearings on the overall performance of an IC device. In some examples, metal gate boundary diffusion may lead to unstable threshold voltage (Vt) when separation distances between the active device regions are reduced to meet design requirements of smaller technology nodes. While methods of reducing parasitic capacitance in IC devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all aspects.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a diagrammatic plan view of an IC structure, in portion or entirety, according to various aspects of the present disclosure.

FIG. 2 is a circuit diagram of a SRAM cell, which can be implemented in a memory cell of a memory macro, according to various aspects of the present disclosure.

FIG. 3 is a diagrammatic plan view of a SRAM cell, which can be implemented in a memory cell of a memory macro, according to various aspects of the present disclosure.

權(quán)利要求

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