Referring to FIG. 5B, which is a cross-sectional view of FIG. 4 taken along line B-B′, i.e., through one of the fins 204 along the X-axis. In the depicted embodiments, each gate stack 620 is disposed between two n-type S/D features 214N along the X-axis, where the top portion 620A of the gate stacks 620 is disposed over the bottom portion 620B, i.e., over the topmost channel layers 207. The bottom portions 620B of the gate stacks 620 are interleaved with the channel layers 207. In the present embodiments, the bottom portions 620B includes the interfacial layer 602 disposed over and wraps around the channel layers 207, the gate dielectric layer 604 disposed over and wraps around the interfacial layer 602, and the WFM layer 606 disposed over the gate dielectric layer 604. The interfacial layer 602, the gate dielectric layer 604, the WFM layer 606, and the portions of the sacrificial layers 205 (optional) completely fill the openings between the channel layers 207 as shown in FIG. 5B. Notably, the bottom portion 620B is free of the metal fill layer 610 as discussed above with respect to FIG. 5A. The top portion 620A includes the interfacial layer 602, the gate dielectric layer 604 disposed over the interfacial layer 602, the WFM layer 606 disposed over the gate dielectric layer 604, and the metal fill layer 610 disposed over the top surface of the WFM layer 606. As discussed above, the device 200 may further include the ESL (not shown) disposed over the top surface of the gate stacks 620 to accommodate subsequent fabrication of components such as the S/D contacts.