At operation 112, referring to FIGS. 11A and 11B, the method 100 forms a dummy gate stack (or a placeholder gate) 220 disposed over the fins 204 and the fins 206. After forming other components (e.g., the n-type S/D features 214N and the p-type S/D features 214P) of the device 200, the dummy gate stacks 220 is removed to form a gate trench in which at least a gate dielectric layer (e.g., the gate dielectric layer 604) and a metal gate electrode (e.g., including the WFM layer 606 and the metal fill layer 610) are subsequently formed to complete the fabrication of the gate stacks 620. Various material layers of the dummy gate stacks 220 may be first deposited as a blanket layer over the semiconductor fins and subsequently patterned, followed by one or more etching process, to form the dummy gate stacks 220 in a desired configuration in the device 200. The various material layers of the dummy gate stacks 220 may be formed by any suitable method, such as chemical oxidation, thermal oxidation, CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, other suitable methods, or combinations thereof.
