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Semiconductor devices with threshold voltage modulation layer

專利號
US12213297B2
公開日期
2025-01-28
申請人
Taiwan Semiconductor Manufacturing Company, Ltd.（TW Hsinchu）
發(fā)明人
Shih-Hao Lin; Chih-Hsiang Huang; Shang-Rong Li; Chih-Chuan Yang; Jui-Lin Chen; Ming-Shuan Li
IPC分類
H01L21/8238; H01L21/02; H01L21/28; H01L29/06; H01L29/423; H01L29/49; H01L29/66; H01L29/786; H10B10/00
技術(shù)領(lǐng)域
layer,fins,wfm,layers,gate,vt,capping,in,channel,stacks
地域： Hsin-Chu

摘要

A method comprises forming a first fin including alternating first channel layers and first sacrificial layers and a second fin including alternating second channel layers and second sacrificial layers, forming a capping layer over the first and the second fin, forming a dummy gate stack over the capping layer, forming source/drain (S/D) features in the first and the second fin, removing the dummy gate stack to form a gate trench, removing the first sacrificial layers and the capping layer over the first fin to form first gaps, removing the capping layer over the second fin and portions of the second sacrificial layers to from second gaps, where remaining portions of the second sacrificial layers and the capping layers form a threshold voltage (Vt) modulation layer, and forming a metal gate stack in the gate trench, the first gaps, and the second gaps.

說明書

FIG. 27 illustrates a flow chart of a method for fabricating an IC device according to various aspects of the present disclosure.

FIGS. 28A and 29A are cross-sectional views of the semiconductor device taken along line A-A′ as shown in FIG. 4 during intermediate stages of the method shown in FIG. 27 according to various embodiments of the present disclosure.

FIGS. 28B and 29B are cross-sectional views of the semiconductor device taken along line B-B′ as shown in FIG. 4 during intermediate stages of the method shown in FIG. 27 according to various embodiments of the present disclosure.

FIG. 30 illustrates a flow chart of a method for fabricating an IC device according to various aspects of the present disclosure.

FIG. 31A is a cross-sectional view of the semiconductor device taken along line A-A′ as shown in FIG. 4 during intermediate stages of the method shown in FIG. 30 according to various embodiments of the present disclosure.

FIG. 31B is a cross-sectional view of the semiconductor device taken along line B-B′ as shown in FIG. 4 during intermediate stages of the method shown in FIG. 30 according to various embodiments of the present disclosure.

權(quán)利要求

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