In the display region DA shown in FIG. 1A, the first, second, and third pixel regions may be arranged in a specific rule. The minimum repetition unit of the first, second, and third pixel regions may be a unit pixel. In an embodiment, the unit pixel may be a region, in which one first pixel region, one second pixel region, and one third pixel region are disposed. In an embodiment, the unit pixel may include one first pixel region, two second pixel regions, and one third pixel region.

A portion of the pixel PX, in which a driving transistor T-D and an emission element OLED are provided, may have a sectional structure as illustrated in FIG. 2A. The display panel DP may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, and a plurality of signal lines. For example, an insulating layer, a semiconductor layer, and a conductive layer may be formed through a coating or deposition process. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by a photolithography and etching process. This method may be used to form the semiconductor patterns, the conductive patterns, and the signal lines constituting the circuit element layer DP-CL and the display element layer DP-OLED.

In the present embodiment, the circuit element layer DP-CL may include a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, and a third insulating layer 30. For example, the buffer layer BFL, the first insulating layer 10, and the second insulating layer 20 may be inorganic layers, and the third insulating layer 30 may be an organic layer.