The network device provided by this embodiment of the present disclosure allocates one or more frequency resources for various messages (such as the random access request and the random access response) in a random access process, so that the frequency resources used for the messages in the random access process do not overlap and that a delay and a failure rate of the random access process are reduced.

In this embodiment of the present disclosure, in FIG. 7, a bus architecture may include any quantity of interconnect buses and bridges, specifically for interconnecting various circuits of one or more processors represented by the processor 601 and a memory represented by the memory 603. The bus architecture may further interconnect various other circuits such as a peripheral device, a voltage regulator, and a power management circuit. These are all well known in the art, and therefore are not further described in this specification. The bus interface provides an interface. The transceiver 602 may be a plurality of components, that is, the transceiver 602 includes a transmitter and a receiver, and provides a unit for communicating with various other apparatuses over a transmission medium. For different user equipment, the user interface 604 may also be an interface for externally or internally connecting a required device, and the connected device includes but is not limited to a mini keyboard, a display, a speaker, a microphone, a joystick, or the like. The processor 601 is responsible for bus architecture management and general processing. The memory 603 may store data used when the processor 601 performs an operation.

In addition, the network device 600 includes some functional modules that are not shown, details of which are not described herein.