The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
FIG. 1 illustrates an exemplary serial loop system;
FIG. 2 illustrates an exemplary parallel loop system;
FIG. 3 illustrates an exemplary reverse-return parallel loop system with two processing units, in accordance with an embodiment of the present invention;
FIGS. 4A-4C illustrate an exemplary reverse-return parallel loop system for four processing units, wherein FIG. 4A shows a block diagram of a reverse-return parallel loop system, FIG. 4B shows a front view of a reverse-return parallel loop system, and FIG. 4C shows a perspective view of a reverse-return parallel loop system, in accordance with an embodiment of the present invention;
FIGS. 5A-5B illustrate exemplary flow paths within a reverse-return parallel loop system, wherein FIG. 5A shows a flow path for a first CPU and FIG. 5B shows a flow path of a second CPU, in accordance with an embodiment of the present invention;
FIG. 6 illustrates an exemplary vertical reverse return system, in accordance with an embodiment of the present invention; and
