Integrated chip with a gate structure disposed within a trench
地域：
Hsinchu
摘要
The present disclosure relates to an integrated chip comprising a substrate having a first pair of opposing sidewalls that define a trench. The trench extends into a front-side surface of the substrate. A first source/drain region is disposed along the front-side surface of the substrate. A second source/drain region is disposed along the front-side surface of the substrate. A gate structure is disposed within the trench and is arranged laterally between the first source/drain region and the second source/drain region. The gate structure fills the trench and extends along the first pair of opposing sidewalls to an upper surface of the substrate. A bottom surface of the gate structure is disposed below a bottom surface of the first source/drain region.
說明書
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This Application is a Divisional of U.S. application Ser. No. 17/459,184, filed on Aug. 27, 2021, the contents of which are hereby incorporated by reference in their entirety.
Flash memory is an electronic non-volatile computer storage medium that can be electrically erased and reprogrammed quickly. It is used in a wide variety of electronic devices and equipment. Common types of flash memory cells include stacked gate memory cells and split gate memory cells. Compared to stacked gate memory cells, split gate memory cells have higher injection efficiency, less susceptibility to short channel effects, and better over erase immunity.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
權(quán)利要求
What is claimed is:1. An integrated chip, comprising:a substrate comprising a first pair of opposing sidewalls that define a trench, wherein the trench extends into a front-side surface of the substrate; a first source/drain region disposed along the front-side surface of the substrate; a second source/drain region disposed along the front-side surface of the substrate; and a gate structure disposed within the trench and arranged laterally between the first source/drain region and the second source/drain region, wherein the gate structure fills the trench and extends along the first pair of opposing sidewalls to an upper surface of the substrate, wherein a bottom surface of the gate structure is disposed below a bottom of the first source/drain region, wherein the gate structure comprises a first gate, a second gate adjacent to the first gate, and a dielectric structure, wherein the dielectric structure continuously laterally extends from an outer sidewall of the first gate to an outer sidewall of the second gate. 2. The integrated chip of claim 1 , wherein the first pair of opposing sidewalls comprises a first sidewall opposite a second sidewall, wherein the first source/drain region extends along the first sidewall and the second source/drain region extends along the second sidewall. 3. The integrated chip of claim 2 , wherein the first and second sidewalls respectively comprise a straight sidewall segment vertically above a curved sidewall segment, wherein the gate structure continuously extends from the straight sidewall segment to the curved sidewall segment of the first and second sidewalls. 4. The integrated chip of claim 1 , wherein a top surface of the gate structure is aligned with the front-side surface of the substrate. 5. The integrated chip of claim 1 , wherein a top surface of the gate structure is vertically below the front-side surface of the substrate. 6. The integrated chip of claim 1 , further comprising:a semiconductor device disposed on the front-side surface of the substrate and laterally offset from the gate structure, wherein the semiconductor device comprises a gate electrode, a gate dielectric layer disposed between the gate electrode and the front-side surface of the substrate, and a pair of source/drain regions disposed within the substrate on opposing sides of the gate electrode, wherein a top surface of the gate structure is disposed vertically below a bottom surface of the gate electrode. 7. The integrated chip of claim 6 , further comprising:an isolation structure extending into the front-side surface of the substrate and laterally between the gate structure and the semiconductor device, wherein the top surface of the gate structure is disposed vertically below a top surface of the isolation structure. 8. An integrated chip, comprising:a substrate having a memory region laterally adjacent to a logic region, wherein the substrate comprises a first pair of opposing sidewalls defining a first trench and a second pair of opposing sidewalls defining a second trench within the memory region; a plurality of source/drain regions disposed along a front-side surface of the substrate, wherein the plurality of source/drain regions comprises a common source/drain region disposed laterally between the first trench and the second trench; a first gate structure disposed within the first trench; a second gate structure disposed within the second trench, wherein the first and second gate structures respectively comprise a first gate and a second gate laterally adjacent to the first gate, wherein a top surface of the first gate and a top surface of the second gate are aligned; and a logic device disposed within the logic region, wherein the logic device comprises a logic gate dielectric layer over the substrate and a logic gate electrode overlying the logic gate dielectric layer; wherein top surfaces of the first and second gate structures are vertically below a bottom surface of the logic gate electrode. 9. The integrated chip of claim 8 , wherein a top surface of the common source/drain region is disposed vertically above the top surfaces of the first and second gate structures. 10. The integrated chip of claim 8 , wherein the first gate and the second gate comprise polysilicon and the logic gate electrode comprises a metal material. 11. The integrated chip of claim 8 , further comprising:a first charge trapping dielectric structure disposed between the substrate and the second gate of the first gate structure, wherein the first charge trapping dielectric structure is U-shaped. 12. The integrated chip of claim 11 , wherein a top surface of the first charge trapping dielectric structure is disposed below a top surface of the logic gate dielectric layer. 13. The integrated chip of claim 8 , further comprising:an isolation structure extending into the front-side surface of the substrate and disposed laterally between the memory region and the logic region; wherein a bottom surface of the first gate structure is disposed vertically between a bottom surface of the common source/drain region and a bottom surface of the isolation structure. 14. An integrated chip, comprising:a substrate comprising a recess extending into a first surface of the substrate; a pair of source/drain regions disposed on opposing sides of the recess; a first gate structure disposed within the recess, wherein the first gate structure comprises a first gate and a second gate laterally offset from the first gate by a non-zero distance; a gate dielectric layer disposed along a first sidewall and a lower surface of the first gate; and a charge trapping dielectric structure disposed along opposing sidewalls and a lower surface of the second gate. 15. The integrated chip of claim 14 , wherein the charge trapping dielectric structure continuously extends from the second gate to a second sidewall of the first gate. 16. The integrated chip of claim 15 , wherein the non-zero distance is equal to a thickness of the charge trapping dielectric structure. 17. The integrated chip of claim 14 , wherein a top surface of the gate dielectric layer is coplanar with a top surface of the charge trapping dielectric structure. 18. The integrated chip of claim 14 , wherein a width of the charge trapping dielectric structure is greater than a width of the gate dielectric layer. 19. The integrated chip of claim 1 , wherein a top surface of the first gate and a top surface of the second gate are aligned with or vertically below the front-side surface of the substrate. 20. The integrated chip of claim 1 , wherein a height of the dielectric structure is greater than a height of the second gate.
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