Integrated chip with a gate structure disposed within a trench
摘要
說明書
The integrated chip 200a includes a first memory cell 202a and a second memory cell 202b disposed laterally within a memory region 102a of the substrate 102. In various embodiments, the substrate 102 may, for example, be or comprise a bulk substrate (e.g., bulk silicon), a silicon-on-insulator (SOI) substrate, or another suitable substrate and/or may comprise a first doping type (e.g., p-type). Further, the substrate 102 comprises a first pair of opposing sidewalls that define the first trench 102t1 and a second pair of opposing sidewalls that define the second trench 102t2. The first trench 102t1 and the second trench 102t2 extend into a front-side surface 102f of the substrate 102 and are laterally offset from one another by a non-zero distance.
