Integrated chip with a gate structure disposed within a trench
摘要
說明書
In various embodiments, the first memory cell 202a comprises a first source/drain region 104a that is disposed along the front-side surface 102f of the substrate 102. The second memory cell 202b comprises a third source/drain region 104c that is disposed along the front-side surface 102f of the substrate 102. Further, the first and second memory cells 202a-b share a second source/drain region 104b that is disposed laterally between the first and third source/drain regions 104a, 104c and is disposed along the front-side surface 102f of the substrate 102. In various embodiments, the second source/drain region 104b may be referred to as a common source/drain region. In further embodiments, the first memory cell 202a comprises the first gate structure 112a disposed laterally between the first and second source/drain regions 104a, 104b, and the second memory cell 202b comprises the second gate structure 112b disposed laterally between the second and third source/drain regions 104b, 104c. In various embodiments, the first, second, and third source/drain regions may comprise a second doping type (e.g., n-type) opposite the first doping type (e.g., p-type).
