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Integrated chip with a gate structure disposed within a trench

專利號(hào)
US12219770B2
公開(kāi)日期
2025-02-04
申請(qǐng)人
Taiwan Semiconductor Manufacturing Company, Ltd.（TW Hsinchu）
發(fā)明人
Yong-Sheng Huang; Ming Chyi Liu
IPC分類
H10B43/30; H01L21/28; H01L29/06; H01L29/08; H01L29/423; H01L29/792; H10B41/30; H10B43/40
技術(shù)領(lǐng)域
gate,dielectric,substrate,region,layer,102t1,102f,102t2,trench,drain
地域： Hsinchu

摘要

The present disclosure relates to an integrated chip comprising a substrate having a first pair of opposing sidewalls that define a trench. The trench extends into a front-side surface of the substrate. A first source/drain region is disposed along the front-side surface of the substrate. A second source/drain region is disposed along the front-side surface of the substrate. A gate structure is disposed within the trench and is arranged laterally between the first source/drain region and the second source/drain region. The gate structure fills the trench and extends along the first pair of opposing sidewalls to an upper surface of the substrate. A bottom surface of the gate structure is disposed below a bottom surface of the first source/drain region.

說(shuō)明書(shū)

In some embodiments, the first gate structure 112a is disposed within the first trench 102t1 such that a top surface of the first gate structure 112a is vertically aligned with the front-side surface 102f of the substrate 102. In further embodiments, the first gate structure 112a is disposed within the first trench 102t1 such that the top surface of the first gate structure 112a is disposed vertically below the front-side surface 102f of the substrate 102 (not shown) (e.g., see FIG. 2E). In various embodiments, the second gate structure 112b is disposed within the second trench 102t2 such that a top surface of the second gate structure 112b is vertically aligned with the front-side surface 102f of the substrate. In yet further embodiments, the second gate structure 112b is disposed within the second trench 102t2 such that the top surface of the second gate structure 112b is disposed vertically below the front-side surface 102f of the substrate (not shown) (e.g., see FIG. 2E).

權(quán)利要求

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