FIG. 2C illustrates a cross-sectional view of some embodiments of an integrated chip 200c corresponding to some alternative embodiments of the integrated chip 200a of FIG. 2A, in which the first and second gate structures 112a, 112b, the first, second, and third source/drain regions 104a, 104b, 104c, and the pair of source/drain regions 130 are covered by silicide layers 204. In various embodiments, the silicide layers 204 may, for example, be or comprise nickel silicide, titanium silicide, or the like. In yet further embodiments, a first silicide layer 204a overlying the first gate 114a is separated from a second silicide layer 204b overlying the second gate 114b by the charge trapping dielectric structure 110. Further, a contact etch stop layer (CESL) 206 is disposed between the ILD layer 116 and the front-side surface 102f of the substrate 102. In some embodiments, the CESL 206 may, for example, be or comprise silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, another dielectric material, or any combination of the foregoing. Further, a sidewall spacer 208 is disposed along opposing sidewalls of the logic gate dielectric layer 128 and along opposing sidewalls of the logic gate electrode 126.
