Integrated chip with a gate structure disposed within a trench
摘要
說(shuō)明書
Many integrated chips include memory cells disposed along a substrate. For example, an integrated chip may comprise a split-gate flash memory cell disposed along a substrate and disposed laterally within a memory region of the substrate. The memory cell includes a first source/drain region and a second source/drain region that are disposed along a horizontal top surface of a substrate and that are laterally separated from each other by a channel region of the substrate. A gate structure is disposed over the top surface of the substrate and is arranged between the first source/drain region and the second source/drain region. The gate structure includes a select gate and a memory gate that is laterally adjacent to the select gate. The select gate is vertically separated from the channel region by a select gate dielectric layer and the memory gate is vertically separated from the channel region by a charge trapping dielectric structure. A length of the channel region is proportional to a length of the top surface of the substrate that extends between the first and second source/drain regions. Further, the integrated chip may include a plurality of logic devices disposed within a logic region of the substrate that is directly adjacent to the memory region of the substrate. The logic devices may each comprise a logic gate disposed over the top surface of the substrate.
