In yet other embodiments, the present disclosure relates to a method for forming an integrated chip, the method includes patterning a front-side surface of a substrate to define a trench extending into the front-side surface; depositing a gate dielectric layer over the substrate such that the gate dielectric layer lines the trench; forming a first gate over the gate dielectric layer and within the trench such that a bottom surface of the first gate is disposed below the front-side surface; depositing a charge trapping dielectric structure within the trench and along the first gate; forming a second gate over the charge trapping dielectric structure and within the trench such that the second gate is adjacent to the first gate; forming a first source/drain region along the front-side surface; and forming a second source/drain region along the front-side surface, wherein the first and second source/drain regions are disposed on opposing sides of the trench; wherein bottom surfaces of the first and second gates are disposed vertically below a bottom surface of the first source/drain region.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.