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Three-dimensional memory device with doped semiconductor bridge structures and methods for forming the same

專利號(hào)
US12225720B2
公開日期
2025-02-11
申請(qǐng)人
SANDISK TECHNOLOGIES LLC（US TX Addison）
發(fā)明人
Ryousuke Itou; Akihisa Sai; Kenzo Iizuka
IPC分類
H10B41/27; H01L21/3213; H01L21/768; H10B41/10; H10B43/10; H10B43/27; H01L23/522; H01L23/532
技術(shù)領(lǐng)域
backside,trench,dielectric,fill,layer,material,tier,73b,structures,bridge
地域： TX TX Addison

摘要

A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. Bridge structures are formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the bridge structure are present within the backside trenches.

說明書

According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, which comprises: forming a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers over a substrate; forming arrays of memory opening through the vertically alternating sequence; forming arrays of memory opening fill structures in the arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements; forming backside trenches laterally extending along a first horizontal direction through the vertically alternating sequence, wherein a plurality of alternating stacks of insulating layers and sacrificial material layers are laterally spaced apart by the backside trenches; forming a set of one or more bridge structures comprising a doped semiconductor material within each of the backside trenches; and replacing the sacrificial material layers with electrically conductive layers while the sets of at least one bridge structure are present within the backside trenches.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a vertical cross-sectional view of a first exemplary structure after formation of semiconductor devices, lower level dielectric layers, lower metal interconnect structures, and in-process source level material layers on a semiconductor substrate according to an embodiment of the present disclosure.

FIG. 1B is a top-down view of the first exemplary structure of FIG. 1A. The hinged vertical plane A-A′ is the plane of the vertical cross-sectional view of FIG. 1A.

權(quán)利要求

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