Manufacturing method of memory structure
地域：
Taichung
摘要
A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.
說明書
This application is a divisional application of and claims the priority benefit of U.S. application Ser. No. 17/306,874, filed on May 3, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The invention relates to a semiconductor structure and a manufacturing method therefore, and particularly relates to a memory structure and a manufacturing method thereof.
Currently, a memory structure has been developed, which includes a transistor and a capacitor coupled to each other. In this memory structure, the capacitor is used as a storage component. Therefore, how to increase the capacitance of the capacitor to improve the electrical performance of the memory device is the goal of continuous efforts.
The invention provides a memory structure and a manufacturing method thereof, which can effectively increase the capacitance of the capacitor structure, thereby improving the electrical performance of the memory device.
權(quán)利要求
What is claimed is:1. A manufacturing method of a memory structure, comprising:providing a substrate, wherein the substrate comprises a memory array region; forming a bit line structure in the memory array region, wherein the bit line structure is located on the substrate; forming a contact structure in the memory array region, wherein the contact structure is located on the substrate on one side of the bit line structure; forming a stop layer in the memory array region, wherein the stop layer is located above the bit line structure; forming a capacitor structure in the memory array region, wherein the capacitor structure passes through the stop layer and is electrically connected to the contact structure, and a bottom surface of the capacitor structure is lower than a bottom surface of the stop layer; and forming the stop layer in the memory array region and the peripheral circuit region, wherein a top surface of the stop layer located in the memory array region is higher than a top surface of the stop layer located in the peripheral circuit region. 2. The manufacturing method of the memory structure according to claim 1 , wherein the substrate further comprises a peripheral circuit region, and the manufacturing method of the memory structure further comprises:forming a sacrificial material layer in the memory array region and the peripheral circuit region; patterning the sacrificial material layer to form sacrificial layers in the memory array region and the peripheral circuit region; and removing the sacrificial layer located in the peripheral circuit region. 3. The manufacturing method of the memory structure according to claim 1 , wherein the stop layer covers the sacrificial layers located in the memory array region, and the manufacturing method of the memory structure further comprises:patterning the stop layer to expose the sacrificial layer located above the contact structure. 4. The manufacturing method of the memory structure according to claim 3 , wherein a method of patterning the stop layer comprises:forming a dielectric structure on the stop layer; forming a patterned mask layer on the dielectric structure; and removing a portion of the dielectric structure and a portion of the stop layer by using the patterned mask layer as a mask to form an opening in the dielectric structure and the stop layer, wherein the opening exposes the sacrificial layer located above the contact structure. 5. The manufacturing method of the memory structure according to claim 4 , further comprising:after patterning the stop layer, removing the sacrificial layer exposed by the opening, and remaining the sacrificial layer located at an edge of the memory array region and not located above the contact structure. 6. The manufacturing method of the memory structure according to claim 5 , wherein after removing the sacrificial layer exposed by the opening, the opening extends toward the substrate to increase a depth of the opening. 7. The manufacturing method of the memory structure according to claim 6 , further comprising:after patterning the stop layer, removing the patterned mask layer. 8. The manufacturing method of the memory structure according to claim 7 , wherein in the process of removing the sacrificial layer exposed by the opening, the patterned mask layer is simultaneously removed. 9. The manufacturing method of the memory structure according to claim 3 , wherein after patterning the stop layer, the stop layer covers the sacrificial layer located at an edge of the memory array region and not located above the contact structure. 10. The manufacturing method of the memory structure according to claim 3 , further comprising:before forming the stop layer, forming a hard mask layer between the sacrificial layers in the memory array region, wherein after forming the stop layer, the stop layer covers the sacrificial layers and the hard mask layer located in the memory array region. 11. The manufacturing method of the memory structure according to claim 10 , whereinthe hard mask layer is located between the stop layer and the bit line structure, the capacitor structure is partially located in the hard mask layer, and a height of the capacitor structure located in the hard mask layer is greater than or equal to one-half of a thickness of the hard mask layer. 12. The manufacturing method of the memory structure according to claim 2 , wherein a method of removing the sacrificial layer located in the peripheral circuit region comprises:forming a patterned photoresist layer, wherein the patterned photoresist layer covers the sacrificial layers located in the memory array region and exposes the sacrificial layer located in the peripheral circuit region; and removing the sacrificial layer located in the peripheral circuit region by using the patterned photoresist layer as a mask. 13. The manufacturing method of the memory structure according to claim 2 , further comprising:before forming the sacrificial material layer, forming a conductive material layer in the memory array region and the peripheral circuit region; and patterning the conductive material layer, so that a first conductive layer located above the contact structure is formed in the memory array region, a dummy conductive layer not located above the contact structure is formed in the memory array region, and a second conductive layer is formed in the peripheral circuit region. 14. The manufacturing method of the memory structure according to claim 13 , wherein after forming the sacrificial layers, the sacrificial layers are respectively located above the first conductive layer, the dummy conductive layer, and the second conductive layer. 15. The manufacturing method of the memory structure according to claim 13 , wherein a top surface of the first conductive layer is the same height as a top surface of the dummy conductive layer. 16. The manufacturing method of the memory structure according to claim 13 , the capacitor structure is electrically connected to the contact structure via the first conductive layer. 17. The manufacturing method of the memory structure according to claim 2 , wherein a top surface of the sacrificial layer is the same height as a bottom surface of the stop layer located above the bit line structure. 18. The manufacturing method of the memory structure according to claim 2 , wherein a material of the sacrificial material layer comprises polysilicon. 19. The manufacturing method of the memory structure according to claim 1 , a material of the stop layer comprises nitride. 20. A manufacturing method of a memory structure, comprising:providing a substrate, wherein the substrate comprises a memory array region; forming a bit line structure in the memory array region, wherein the bit line structure is located on the substrate; forming a contact structure in the memory array region, wherein the contact structure is located on the substrate on one side of the bit line structure; forming a stop layer in the memory array region, wherein the stop layer is located above the bit line structure; and forming a capacitor structure in the memory array region, wherein the capacitor structure passes through the stop layer and is electrically connected to the contact structure, and a bottom surface of the capacitor structure is lower than a bottom surface of the stop layer, wherein the substrate further comprises a peripheral circuit region, and the manufacturing method of the memory structure further comprises: forming a sacrificial material layer in the memory array region and the peripheral circuit region; patterning the sacrificial material layer to form sacrificial layers in the memory array region and the peripheral circuit region; and completely removing the sacrificial layer located in the peripheral circuit region.
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