FIG. 5 is a schematic cross-sectional diagram of a structure after a recess is formed in a semiconductor buffer layer according to one embodiment of the present disclosure. Referring to FIG. 5, a semiconductor buffer layer 104, a semiconductor channel layer 106, a semiconductor barrier layer 108, and a gate capping layer 110 may be sequentially formed on a substrate 102 to obtain a semiconductor structure 100-5. Thereafter, a patterned mask 140 may be formed, and the semiconductor barrier layer 108, the semiconductor channel layer 106, and the semiconductor buffer layer 104 exposed from the patterned mask 140 may be etched to form a recess 142. The recess 142 may expose the sidewall 108S of the semiconductor barrier layer 108, the sidewall 106S of the semiconductor channel layer 106, and the vertical surface 105S and the horizontal surface 105T of the semiconductor buffer layer 104. Subsequently, the patterned mask 140 may be further removed.