FIG. 1 is a schematic cross-sectional diagram of a semiconductor device according to one embodiment of the present disclosure. Referring to FIG. 1, a semiconductor device 100-1 includes at least a substrate 102, a semiconductor channel layer 106, a semiconductor barrier layer 108, a gate electrode 112, and a dielectric layer 116. The semiconductor channel layer 106 is disposed on the substrate 102, the semiconductor barrier layer 108 is disposed on the semiconductor channel layer 106, and the gate electrode 112 is disposed on the semiconductor barrier layer 108. The first electrode 120 is disposed at one side of the gate electrode 112, where the first electrode 120 may include a body portion 122, a vertical extension portion 126, and an optional horizontal extension portion 124. The body portion 122 may be electrically connected to the vertical extension portion 126 and the horizontal extension portion 124, and the body portion 122 may be electrically connected to the semiconductor barrier layer 106. A bottom surface 126B of the vertical extension portion 126 is lower than a top surface 106T of the semiconductor channel layer 106. In addition, the dielectric layer 116 may be disposed between the vertical extension portion 126 and the semiconductor channel layer 106. Furthermore, according to one embodiment of the present disclosure, the semiconductor device 100-1 may further include a buffer layer 104, a gate capping layer 110 and a second electrode 130. The semiconductor buffer layer 104 may be disposed between the substrate 102 and the semiconductor channel layer 106, which may be used to reduce leakage current between the substrate 102 and the semiconductor channel layer 106, or to reduce stress accumulation or lattice mismatch between the substrate 102 and the semiconductor channel layer 106. The gate capping layer 110 may be disposed between the semiconductor barrier layer 108 and the gate electrode 112. The first electrode 120 and the second electrode 130 may be disposed at both sides of the gate electrode 112, respectively. According to one embodiment of the present disclosure, a two-dimensional electron gas (2-DEG) may be generated at the junction of the semiconductor channel layer 106 and the semiconductor barrier layer 108. By providing the gate capping layer 110, two-dimensional electron gas will not be generated in the corresponding semiconductor channel layer 106 below it, so that part of the two-dimensional electron gas will be cut off.